1. Field of the Invention
The present invention generally relates to a digital level display device. It particularly relates to a digital level display device effectively used in a compact disk (CD) player, a digital audio tape recorder (DAT), or the like.
2. Background of the Invention
In a PCM recording/reproducing apparatus such as a CD player, a DAT, or the like, an analog audio signal is digitized so as to be recorded on a recording medium. During reproducing, on the other hand, a reproduced digital signal is converted into an analog signal which is sent out as an output. FIG. 2 is a block diagram showing an example of the conventional digital level display device used, for example, for monitoring a level of a digital signal in such a PCM recording/reproducing apparatus as described above.
In the drawing, a conversion circuit 1 converts a signal applied thereto into an absolute value signal representing an absolute value of the digital signal. The absolute value signal produced from the conversion circuit 1 is applied to a peak latch circuit 2 constituted by a register 3 and a comparator 4 so that a peak value of the absolute value signal is detected and latched. A CPU 5 reads the latched value of the peak latch circuit 2 at a predetermined timing, logarithmically converts the readout latched value into a value for indication in decibels (dB), and further converts the logarithmically converted value into a display signal suitable to be displayed. The CPU 5 applies the display signal to a display 8 constituted by a plurality of lamps, a plurality of light emitting diodes (LEDs), or the like, so as to cause the display 8 to display the peak level of the digital signal.
A reset switching device 6 is arranged so that if the reset switching device 6 is turned on, the CPU 5 controls the register 3 so as to clear the peak value latched in the register 3. A selector 7 is arranged so that if the selector 7 is operated, routines having different resolutions in a program of the CPU 5 are changed over from one to another so that the display resolution in the display 8 can be changed, for example, from a resolution of 3 dB to another resolution of 1 dB, or the like.
The CPU 5 is arranged to operate and process a signal on the basis of the program. Therefore, it takes a long time for the CPU 5 to perform a conversion operation in comparison with a period of sampling data. Accordingly, the CPU 5 causes the peak latch circuit 2 to latch the data for a time required for the operation and causes the peak latch circuit 2 to clear the latched value when the CPU 5 has read the data.
Thus, in the conventional digital level display device, the logarithmic conversion as well as the conversion into the display signal are performed by the CPU 5. Therefore, it is necessary to transfer all the bits representing an absolute value of data to the CPU 5. Therefore, there has been such a disadvantage that not only is a load of the CPU 5 made large but also the number of data lines is increased when data is transferred in parallel to the CPU 5 or the transfer time is increased when data is serially transferred to the CPU 5. Further, there has been a further disadvantage that the arrangement of the peak latch circuit becomes complicated.